The invention concerns a transmission line for delivery of high-frequency clock signals.
FIG. 1 illustrates a clock 3 which feeds a clock signal to a transmission line 6, which may take the form of a trace on a printed circuit board (not shown). The trace 6 leads to a clocked device 9, which uses the clock signal as an input.
At low clock frequencies, the apparatus shown encounters no significant problems. For example, when the line 6 is 15.12 inches long, and the clock runs at 33 MHz, clock signal 12 delivered to the clocked device 9 was found to be acceptable, as indicated.
However, if the clock frequency is increased, problems can be encountered. For example, if the clock signal is increased to 66 MHz, as in FIG. 2, then the clock signal 16, measured at the input 17 of device 9A, was found to be unacceptable, as indicated. FIG. 3 illustrates specific defects found in the clock signal.
When the clock signal was supposed to be LOW, as in region 18 in FIG. 3, it failed to remain below the upper limit 20 of the LOW region, as excursions 23 and 26 indicate. When the clock signal was supposed to be HIGH, as in region 29, it failed to remain above the lower limit 33 of the HIGH region, as excursions 36 and 39 indicate.
These defects render the clock signal 16 unacceptable for many purposes.
An object of the invention is to provide an improved clock signal in a digital system.
In one form of the invention, the transmission line carrying the clock signals is lengthened, in order to cause the reflected impedance of the clocked device, seen by the clock, to be both high and capacitive. For a clocked device having an input capacitance of about 5 to 20 pico-Farads, a line length of about xc2xd wavelength of the clock pulses provides satisfactory results.